by Keysight Technologies
A machine learning-driven extraction workflow has cut BSIM4 MOSFET parameter extraction from more than 100 steps to five or six, validated across 36 device geometries and over 80 simultaneously optimized parameters. A comparable workflow for the VBIC bipolar model reduced extraction to three steps and reached a global optimum in a single day. Both results point to the same shift: in semiconductor device modeling, AI and machine learning are replacing slow, manual extraction with automated workflows that compress weeks of engineering time into days, without sacrificing fitting accuracy.
The pressure behind this shift is structural. As traditional scaling approaches its physical and economic limits, innovation now depends on Gate-All-Around transistors, wide-bandgap materials such as GaN and SiC, and heterogeneous integration through chiplets, 3D stacking, and System-in-Package design, all of which demand tighter coupling between process, device, and system-level performance under Design Technology Co-Optimization (DTCO).
Device modeling sits at the center of that coupling, and it is increasingly strained. Traditional physics-based frameworks provide a foundation, but they struggle to capture the nonlinear dynamics, quantum effects, and multiphysics interactions inherent in modern devices; simplified equations often miss nanoscale phenomena such as quantum tunneling, self-heating, and variability, which reduces predictive accuracy for emerging technologies. Parameter extraction compounds the problem. As model dimensionality grows, tuning hundreds or thousands of interdependent parameters by hand becomes slow, iterative, and error-prone, particularly as geometry, temperature, and process conditions vary and the work falls to a shrinking pool of domain experts.
AI and ML address both halves of that problem. Neural networks and hybrid architectures support the rapid development of surrogate models for advanced technologies, reducing the need for extensive parameter extraction, while ML-driven extraction methods simplify modeling workflows directly, often cutting the number of extraction steps from hundreds to fewer than ten. The benchmark studies described in this article show modeling timelines shrinking from weeks to days, high-fidelity results across DC, RF, and large-signal domains, and faster delivery of Process Design Kits (PDKs).
Large Language Models (LLMs) are emerging as a complementary tool within Electronic Design Automation (EDA). Their ability to interpret and generate technical content supports model template creation, simulation scripting, documentation, and parameter-tuning strategies, and when integrated with cloud-based platforms, they extend real-time collaboration and workflow automation to design teams working across locations.
AI/ML for Device Modeling
AI and ML are changing semiconductor device modeling by offering fast, data-driven alternatives to traditional physics-based workflows. Deep learning, in particular, has become an effective tool for capturing the highly nonlinear relationships in device behavior. Instead of solving differential equations, neural networks approximate IV, CV, and QV characteristics with high accuracy and reduced computational cost. Several architectures are widely used in device modeling.
Feedforward Neural Networks (FNNs) are a straightforward yet effective architecture for semiconductor device modeling. They map operating conditions to electrical outputs through layers of nonlinear transformations, using a one-way flow without feedback loops, which makes FNNs efficient at capturing complex static relationships and often allows them to outperform traditional compact models in accuracy and flexibility.
Physics-Informed Neural Networks (PINNs) embed equations such as Poisson’s or continuity equations into the loss function, ensuring physical consistency even with limited or noisy training data.
Recurrent Neural Networks (RNNs) are specialized for sequential data, where the output at each step depends on previous inputs. In semiconductor modeling, RNNs are useful for capturing time-dependent behaviors such as transient responses or dynamic switching events; their feedback loops allow the network to retain memory of past states, enabling it to model processes that evolve over time.
Parameter extraction, a major bottleneck in modeling, also benefits from AI/ML. Modern compact models can include thousands of parameters, making traditional iterative tuning slow and sensitive to initialization. ML-based extractors provide faster, more scalable alternatives.
Neural network-based parameter mapping learns a direct relationship between device curves and model parameters, avoiding derivative-based optimization and improving robustness against local minima. One promising architecture is the autoencoder-based extractor, which compresses device data into a latent space and then reconstructs it while simultaneously linking the latent representation to model parameters.
Gradient-based methods incorporate ML techniques into numerical optimization, using gradients to efficiently minimize error between measured and modeled characteristics. These methods are fast but require careful regularization to handle highly nonlinear regions.
Derivative-free optimization (DFO) is well suited to parameter extraction when gradients are unavailable or unreliable in highly nonlinear or discontinuous spaces. Rather than relying on derivatives, these methods use iterative search strategies that handle non-smooth objective functions and complex compact models with strong robustness to local minima. DFO techniques are generally more evaluation-intensive than gradient-based methods, but they support multi-objective extraction and perform reliably across challenging parameter landscapes.
Reinforcement Learning (RL) is well suited to sequential decision-making problems, in which an agent interacts with an environment by taking actions to maximize cumulative long-term reward. Unlike supervised learning, RL must handle uncertainty, delayed rewards, and the exploration-exploitation trade-off. It is widely applied in domains such as robotics and autonomous driving, where environments are dynamic and short-term rewards may not indicate optimal behavior. As with many AI algorithms applied to parameter extraction, the high dimensionality of the parameter space remains a major bottleneck for RL as currently applied.
AI and ML provide scalable solutions for both device behavior modeling and compact model parameter extraction, and most of the benefit shows up as less manual effort, improved robustness, and faster deployment of next-generation technologies.
Neural Network-Based Modeling
Neural network-based modeling is an effective approach for advanced semiconductor technologies, particularly during early development stages when no mature compact model is available. By learning directly from experimental data, neural network models eliminate the need for complex analytical derivations and manual parameter extraction, enabling faster and more flexible model creation.
Applications such as NeuroFET and DynaFET have demonstrated strong performance, and the approach has since evolved into a framework applicable across a broad range of device types.
In the case of GaAs pHEMT devices, for example, separate neural network circuit components were trained on measured data to model the drain and gate currents and charges, then integrated into a Verilog-A framework. The IV characteristics and S-parameters predicted by the neural network model showed close agreement with measurement: both the IV characteristics and small-signal parameters matched consistently, confirming the model’s potential for compound semiconductor devices.
The result is faster model generation for device and circuit evaluation, with complex nonlinear behavior captured directly from data rather than from explicit physical equations.
Hybrid Neural Network Modeling
Hybrid neural network applications have been demonstrated in numerous publications and in practice, for devices including power MOSFETs, III-V transistors, and FinFETs. The approach can address the limitations of industry-standard models and improve modeling accuracy within a shorter development cycle. Unlike a purely data-driven neural network, the hybrid method retains the physical foundation of traditional models, which improves interpretability of device characteristics and stability as devices are scaled.
One practical application is modeling the reverse recovery behavior of IGBT devices under various bias conditions. This behavior, validated using the industry-standard Double Pulse Test (DPT), is critical for predicting transient current surges during device switching.
Conventional models describe reverse recovery with nonlinear differential equations that struggle to hold accuracy across varying bias and temperature. The hybrid approach instead uses neural networks to model key parameters, such as charge storage and release time constants, as functions of voltage, current, and temperature, then incorporates those modules into the compact model so it adapts dynamically to operating conditions.
The resulting fit to the reverse recovery waveform improved markedly, particularly the rising edge, peak current, and falling behavior, across a wide range of voltages, with the largest gains at 500 V and 600 V. Taken together, this case illustrates the broader pattern in hybrid modeling: combining physics-based models with data-driven learning captures effects beyond what traditional formulations reach, improves fitting accuracy for nonlinear and transient behavior, and shortens model development time.
ML-Driven Model Parameter Extraction
ML-driven modeling simplifies device modeling even for engineers with limited experience. As device dimensions shrink, short-channel effects and other complex phenomena become more pronounced, and engineers must balance extraction effort, accuracy, and their own expertise, often relying on years of experience to navigate the trade-offs.
The objective is a repeatable, reliable extraction flow that minimizes development time. Automated, streamlined workflows reduce the risk of manual error and accelerate the modeling process, supporting faster and more consistent device development across technology generations.
Unlike traditional gradient-based algorithms, which can get stuck in local minima, derivative-free algorithms search the full parameter space for a global solution. They apply across a wide range of device types, provided the underlying model captures the key characteristics, automating the search for optimal parameters and reducing manual tuning while improving accuracy and robustness.
A comprehensive MOSFET modeling workflow built on the BSIM4 model illustrates the scale of the improvement: the project covers 36 device sizes and requires only 5 to 6 streamlined steps, compared with the 100-plus steps typical of a traditional flow. During fitting, more than 80 model parameters are optimized simultaneously to capture Id-Vd, Id-Vg, and gm-Vg characteristics. The workflow demonstrated robust performance across all device sizes, along with its efficiency, repeatability, and ability to handle device scaling with minimal development time.
A second application, the VBIC model for bipolar transistors, shows a similar gain. Traditional modeling of these devices requires numerous interdependent parameters and fragmented extraction steps, a complex and time-consuming process. ML optimization streamlines this workflow to three key steps and locates the global optimum in a single day, reducing manual intervention while improving accuracy.
The ML-driven method extends to other device types and models as well, including III-V and FinFET devices, with a consistent gain in efficiency and consistency. Across these cases, the new ML-driven modeling cuts extraction from hundreds of steps to five or six, automates the process with minimal manual effort and fewer errors, adapts readily to different device types and compact models, and reduces dependence on user expertise, so both beginners and experienced engineers can reach high-quality fits.
DynaFET Model
To demonstrate the advantages of the neural network-based model, a benchmark was established based on the DynaFET model, focusing on predictive accuracy, robustness, and simulation efficiency. The benchmark employed a 150 nm, 6 × 60 µm GaN HFET from Raytheon Integrated Defense Systems, a device used for power amplifier, low-noise amplifier, and switch applications across the 1 to 40 GHz range. Model extraction used large-signal data at 100 MHz and S-parameter data at 3.5 GHz from the NVNA setup.
DC validation: The DynaFET model reproduces measured DC characteristics at 55° C with high fidelity, capturing nonlinear drain current, gate leakage behavior, and turn-on characteristics that are typically difficult for analytical compact models to reproduce. The neural network captures these effects by learning coupled electro-thermal and trap-related dynamics directly from the data.
Broadband S-parameters: the model agrees closely with measurements from 500 MHz to 50 GHz, since dynamic charge and dispersion effects are learned implicitly from the training data rather than modeled explicitly.
Large-signal and power performance: Comparing gain compression, bias current, Power-Added Efficiency (PAE), and harmonic distortion under large-signal excitation, the DynaFET model accurately predicts both the magnitude and shape of compression and harmonic trends up to 7 dB of gain compression, while traditional models typically diverge at high power because of fixed functional assumptions and missing dynamic terms.
Two-tone intermodulation and load-pull: Modeled and measured results for third- and fifth-order Intermodulation Distortion (IMD) and load-pull metrics show that the neural network-based model captures nonlinear interactions and dynamic self-heating effects without additional parameter re-extraction, with agreement holding across a wide range of bias conditions and frequencies.
The benchmark shows that the neural network-based DynaFET model provides accuracy, robustness, and usability advantages for this 150 nm, 6 × 60 µm GaN HFET. By learning device behavior directly from measurement, it eliminates repetitive tuning cycles, improves predictive capability across a wide operating range, and streamlines RF and power electronics design workflows.
Hybrid ASM-HEMT Model
This benchmark compares a hybrid modeling workflow, combining a neural network module with the ASM-HEMT physical model, against a baseline using ASM-HEMT alone, to evaluate the improvement in fitting accuracy.
The benchmark uses a GaN-on-SiC HEMT device with a 150 nm gate length and a total gate width of 4 × 50 µm. The ASM-HEMT model (version 101.4) provides accurate DC fitting with strong physical interpretability. Under bias conditions of VD swept up to 25 V and VG = −3 to −1 V, and across a frequency range of 250 MHz to 50 GHz, the baseline S-parameter fit showed noticeable deviation.
To improve high-frequency accuracy, a hybrid ASM-HEMT neural network model was developed by adding three capacitances and two resistances to the ASM-HEMT baseline. This hybrid model substantially improves the agreement between measured and simulated S-parameters, with good fitting accuracy across the entire frequency range.
Measured and simulated Pout, PAE, and dynamic load lines (ΔPin = 3 dBm) at a fundamental frequency of 10 GHz with ZS = 50 Ω and ZL = 87.2 + j71.3 Ω, biased at VD = 20 V and VG = −2 V, show that the simulation using load-dependent X-parameters with the hybrid ASM-HEMT neural network model aligns well with the nonlinear measurements from the NVNA setup. The baseline ASM-HEMT model, without modification, is less accurate for the gain curve and dynamic load lines, and the same gap shows up in S-parameters across a wide range of bias conditions.
Hybrid neural network modeling combines the data-driven adaptability of neural networks with the robustness of physical models, giving a scalable and flexible approach to device modeling. It enables faster model development, improved accuracy, and preservation of physical integrity.
ML-Driven BSIM4 Modeling
To evaluate the ML-driven modeling flow, a benchmark was conducted using the BSIM4 model, assessing improvements in extraction complexity, fitting accuracy, and workflow robustness across device geometries and operating conditions.
Both optimization flows were tested under identical initial conditions, using the same measured IV datasets and parameter initial settings, across 36 devices of both large and small sizes and more than 80 parameters. The ML-driven flow applied a gradient-free global search strategy, while the traditional flow used a gradient-based local optimization algorithm; each aimed to best fit Id-Vd, gds-Vd, Id-Vg, and gm-Vg characteristics across multiple bias regions and device sizes.
Key Takeaways
The ML-driven flow automates parameter extraction and reduces process complexity, producing a more intuitive and productive workflow. It allows engineers to reuse or adapt modeling flows quickly for new or similar device types, and its global optimization makes it straightforward to define parameter ranges, initial values, and fitting regions while still reaching stable, globally optimal results. Because it requires less deep modeling knowledge than the traditional flow, engineers across experience levels can reach consistent, high-quality outcomes, and its Python integration within Keysight’s EDA platform lets engineers automate and customize extraction flows without advanced programming skills.
Conclusion
As the semiconductor industry moves into an era defined by heterogeneous integration, novel device architectures, and system-level co-optimization, the demands on modeling frameworks have grown accordingly. Traditional modeling approaches are increasingly strained by the complexity, scale, and speed that modern design environments require. This article has outlined how AI and ML are changing the landscape of semiconductor device modeling: neural network-based models that remove the need for manual parameter tuning, hybrid neural network architectures that combine physical insight with data-driven adaptability, and ML-powered modeling workflows that together produce faster, more accurate, and more scalable modeling solutions.
The applications and benchmarks presented here show that AI/ML-based modeling improves predictive accuracy across DC, RF, and large-signal regimes, reduces development time, improves generalization across device variants, and lowers the barrier to entry for model developers. These gains align closely with the goals of DTCO, supporting tighter integration among devices, circuits, and system design.